1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing an interconnect.
2. Description of the Related Art
Due to the increasingly high integration of ICs, chips simply cannot provide sufficient area for manufacturing interconnections. Therefore, in accord with the increased interconnect manufacturing requirements of miniaturized MOS transistors, it is increasingly necessary for IC manufacturing to adopt a design with more than two metal layers. In particular, a number of multi-function products, such as microprocessors, may even require 4 or 5 metal layers to complete the internal connections thereof. Generally, an inter-metal dielectric (IMD) layer is used to isolate electrically two adjacent metal layers from each other.
In order to perform an interconnection more easily and to transfer the pattern more precisely, it is important to have a wafer with an even topography. Since the probability of inaccuracy of the alignment system can be reduced by using a wafer with a relatively even topography, the fine pattern can be transferred more accurately.
FIGS. 1A through 1B are schematic, cross-sectional views of the conventional pattern transfer process.
As shown in FIG. 1A, a substrate having a conductive layer 120, wires 120a and 120b and a insulating layer 122 formed thereon is provided. A dotted line I--I divides a wafer (not shown) into two parts. One side of the dotted line I--I, denoted as region 116, is the interior region of the wafer, wherein the interior region has effective dies. The other side of the dotted line I--I, denoted as region 118, is the edge region of the wafer. The dies in the region 118 are incompletely formed, so that the region 118 is a region having ineffective dies. Since the distribution density of the conductive layer 120 is higher than that of the wires 120a and 120b, the ability of portions of the insulating layer 122 in the region 118 to resist the planarization step is higher than that in the region 116. Hence, portions of the insulating layer 122 in the region 118 are thicker than the portions of the insulating layer 122 in the region 116 after chemical-mechanical polishing (CMP). Because the region 118 is higher than the region 116, a sloped surface 124 of the insulating layer 122 above the wire 120a is shown in the region 116 adjacent to the region 118. In highly integrated ICs, the interconnection is more than one layer, so that the step height between the regions 118 and 116 is increasingly larger.
As shown in FIG. 1B, a photoresist 128 is formed on the insulating layer 122. Photolithography is performed to form openings 130a and 130b in the photoresist 128, respectively aligned with the wires 120a and 120b. The opening 130b may be formed to expose the underlying dielectric layer 122 since the photoresist 128 is within the range of depth of focus (DOF). The DOF range is from the optimum focus BF to the maximum AF at both sides of the optimum focus BF. As the portion of the photoresist 128 over the wire 120a is higher and beyond the DOF, so that an error occurs for the photolithography process. As a consequence, the opening 130a fails to expose by the dielectric layer 122. This is called scumming. Additionally, the defocusing happens since a conductive layer subsequently formed on the region 118 is relatively high and beyond the DOF. Therefore, the conductive layer caves.
Generally, the step height of the photoresist caused by the profile of only one conductive layer is about 1000-3000 angstroms, which is an allowable error range. In other words, difference between the photoresist 128 in the region 118 and in the region 116 is about 1000-3000 angstroms. However, the step height increases as the number of the conductive layers increases. Therefore, the step height is more than 6000-7000 angstroms beyond the tolerable range. Hence, the scumming easily happened and it is difficult to accurately transfer a fine pattern from the photomask to the wafer.